Freescale Semiconductor /MKW21Z4 /XCVR_ANALOG_REGS /BB_LDO_2

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as BB_LDO_2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)BB_LDO_PD_BYP 0 (0)BB_LDO_PD_DIAGSEL 0BB_LDO_PD_SPARE 0 (0)BB_LDO_PD_TRIM 0BB_LDO_VCO_SPARE 0 (0)BB_LDO_VCOLO_BYP 0 (0)BB_LDO_VCOLO_DIAGSEL 0 (0)BB_LDO_VCOLO_TRIM 0 (0)BB_LDO_VTREF_DIAGSEL 0 (0)BB_LDO_VTREF_TC

BB_LDO_VCOLO_TRIM=0, BB_LDO_PD_TRIM=0, BB_LDO_VCOLO_DIAGSEL=0, BB_LDO_VTREF_TC=0, BB_LDO_VTREF_DIAGSEL=0, BB_LDO_PD_DIAGSEL=0, BB_LDO_PD_BYP=0, BB_LDO_VCOLO_BYP=0

Description

RF Analog Baseband LDO Control 2

Fields

BB_LDO_PD_BYP

rmap_bb_ldo_pd_byp

0 (0): Bypass disabled.

1 (1): Bypass enabled

BB_LDO_PD_DIAGSEL

rmap_bb_ldo_pd_diagsel

0 (0): Diag disable

1 (1): Diag enable

BB_LDO_PD_SPARE

rmap_bb_ldo_pd_spare[1:0]

BB_LDO_PD_TRIM

rmap_bb_ldo_pd_trim[2:0]

0 (0): 1.20 V ( Default )

1 (1): 1.25 V

2 (2): 1.28 V

3 (3): 1.33 V

4 (4): 1.40 V

5 (5): 1.44 V

6 (6): 1.50 V

7 (7): 1.66 V

BB_LDO_VCO_SPARE

rmap_bb_ldo_vco_spare[1:0]

BB_LDO_VCOLO_BYP

rmap_bb_ldo_vcolo_byp

0 (0): Bypass disabled.

1 (1): Bypass enabled

BB_LDO_VCOLO_DIAGSEL

rmap_bb_ldo_vcolo_diagsel

0 (0): Diag disable

1 (1): Diag enable

BB_LDO_VCOLO_TRIM

rmap_bb_ldo_vcolo_trim[2:0]

0 (0): 1.138/1.117 V ( Default )

1 (1): 1.076/1.058 V

2 (2): 1.027/1.012 V

3 (3): 0.98/0.97 V

4 (4): 1.22/1.19 V

5 (5): 1.33/1.3 V

6 (6): 1.5/1.4 V

7 (7): 1.82/1.4 V

BB_LDO_VTREF_DIAGSEL

rmap_bb_ldo_vtref_diagsel

0 (0): Diag disable

1 (1): Diag enable

BB_LDO_VTREF_TC

rmap_bb_ldo_vtref_tc[1:0]

0 (0): 1.117/1.176 V

1 (1): 1.134/1.188 V

2 (2): 1.10/1.162 V

3 (3): 1.09/1.152 V

Links

() ()